zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 99

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

14.0
14.1
14.1.1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
G
AH
AJ
1
LA_CL
K
AGND
SCLK
AVCC
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
M0_TX
EN
M0_R
XD1
M1_TX
EN
1
2
LA_D1 LA_D3 LA_D6 LA_D9
LA_D0 LA_D2 LA_D5 LA_D8
LA_D1
7
LA_D1
6
RESIN
_
RESE
TOUT_
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
M0_TX
D0
M0_R
XD0
M1_TX
D0
M1_R
XD0
2
BGA Views (TOP-View)
BGA and Ball Signal Descriptions
Encapsulated View In Unmanaged Mode
3
LA_D4 LA_D7
LA_D1
9
LA_D1
8
SCAN
EN
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
T_MO
DE0
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
M0_T
XD1
M0_C
RS
M1_T
XD1
M1_C
RS
M1_R
XD1
3
4
LA_D2
1
LA_D2
0
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
M3_T
XD1
M3_T
XD0
M2_T
XD1
M2_T
XD0
M2_T
XEN
4
5
LA_D1
0
LA_D2
3
LA_D2
2
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
M3_TX
EN
M3_C
RS
M2_C
RS
M2_R
XD0
M2_R
XD1
5
6
LA_D
13
LA_D
12
LA_D
11
LA_D
25
LA_D
24
VCC
VCC
VCC
VCC
VCC
M3_R
XD0
M3_R
XD1
M4_T
XD1
6
M4_T
XD0
M4_T
XEN
7
LA_D
15
LA_D
14
LA_A
3
LA_D
27
LA_D
26
M5_T
XD1
M5_T
XD0
M4_C
RS
M4_R
XD0
M4_R
XD1
7
8
LA_A
4
LA_A
DSC_
LA_O
E_
LA_D
29
LA_D
28
M5_T
XEN
M5_C
RS
M6_T
XD1
M6_T
XD0
M6_T
XEN
8
9
LA_O
E0_
LA_O
E1_
LA_W
E_
LA_D
31
LA_D
30
M5_R
XD0
M5_R
XD1
M6_C
RS
M6_R
XD0
M6_R
XD1
9
10
LA_A
8
LA_A
7
T_M
ODE1
LA_A
6
LA_A
5
VDD
VDD
VDD
VDD
M8_T
XD1
M8_T
XD0
M7_T
XD1
M7_T
XD0
M7_T
XEN
10
11
LA_A
13
LA_A
12
LA_A
11
LA_A
10
LA_A
9
M8_T
XEN
M8_C
RS
M7_C
RS
M7_R
XD0
M7_R
XD1
11
12
LA_A
16
LA_A
15
LA_A
14
LA_W
E0_
LA_W
E1_
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
M8_R
XD0
M8_R
XD1
M9_T
XD1
M9_T
XD0
M9_T
XEN
12
Zarlink Semiconductor Inc.
13
LA_A
19
LA_A
18
LA_A
17
LA_D
49
LA_D
48
VCC
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VCC
M10_
TXD1
M10_
TXD0
M9_C
RS
M9_R
XD0
M9_R
XD1
13
ZL50416
14
LA_D
33
LA_D
32
LA_A
20
LA_D
51
LA_D
50
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
M10_
TXEN
M10_
CRS
M11_
TXD1
M11_
TXD0
M11_
TXEN
14
15
LA_D
36
LA_D
35
LA_D
34
LA_D
53
LA_D
52
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
M10_
RXD0
M10_
RXD1
M11_
CRS
M11_
RXD0
M11_
RXD1
15
99
16
LA_D
39
LA_D
38
LA_D
37
LA_D
55
LA_D
54
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
M13_
TXD1
M13_
TXD0
M12_
TXD1
M12_
TXD0
M12_
TXEN
16
17
LA_D4
2
LA_D4
1
LA_D4
0
LA_D5
7
LA_D5
6
VCC
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VCC
RESE
RVED
M13_
CRS
M12_
CRS
M12_
RXD0
M12_
RXD1
17
18
LA_D
45
LA_D
44
LA_D
43
LA_D
59
LA_D
58
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
M15_
TXD1
M13_
RXD1
M14_
TXD1
M14_
TXD0
M14_
TXEN
18
19
OE_
CLK0
OE_
CLK1
OE_
CLK2
LA_D6
1
LA_D6
0
RESE
RVED
M14_
CRS
M15_
TXD0
M14_
RXD0
M14_
RXD1
19
20
LA_
CLK0
LA_
CLK1
LA_
CLK2
LA_D6
3
RESE
RVED
VDD
VDD
VDD
VDD
M15_
TXEN
RESE
RVED
RESE
RVED
M13_
RXD0
RESE
RVED
20
21
TRUN
K1
LA_D6
2
P_D
LA_D4
7
LA_D4
6
M15_
RXD0
M15_
RXD1
RESE
RVED
M15_
CRS
M13_
TXEN
21
22
RESE
RVED
RESE
RVED
TRUN
K0
SCAN
COL
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
22
23
RESE
RVED
RESE
RVED
RESE
RVED
SCAN
CLK
SCAN
LINK
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
23
24
SCL
RESE
RVED
RESE
RVED
TSTO
UT14
TSTO
UT15
VCC
VCC
VCC
VCC
VCC
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
24
25
SDA
RESE
RVED
AUTO
FD
TSTO
UT13
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
25
26
STRO
BE
D0
TSTO
UT11
TSTO
UT12
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
26
Data Sheet
27
TSTO
UT7
TSTO
UT8
TSTO
UT9
TSTO
UT10
SCAN
MODE
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
27
28
TSTO
UT3
TSTO
UT4
TSTO
UT5
TSTO
UT6
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
MDIO
MDC
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
28
29
TSTO
UT0
TSTO
UT1
TSTO
UT2
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
M_CL
K
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
29