zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 57

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.4
13.4.1
I
Accessed by CPU, serial interface and I
13.4.2
I
Accessed by CPU, serial interface and I
13.4.3
I
Accessed by CPU, serial interface and I
In Port Based VLAN Mode
This register indicates the legal egress ports. A “1” on bit 7 means that the packet can be sent to port 7. A “0” on
bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1 and 3 to form
a 17 bit mask to all egress ports.
In Tag based VLAN Mode
This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form a default VLAN
tag. If the received packet is untagged, then the packet is classified with the default VLAN tag. If the received
packet has a VLAN ID of 0, then PVID is used to replace the packet’s VLAN ID.
13.4.4
I
Accessed by CPU, serial interface and I
In Port based VLAN Mode
2
2
2
2
C Address 036; CPU Address:h100
C Address 037; CPU Address:h101
C Address 038, CPU Address:h102
C Address h53, CPU Address:h103
(Group 1 Address) VLAN Group
AVTCL – VLAN Type Code Register Low
AVTCH – VLAN Type Code Register High
PVMAP00_0 – Port 00 Configuration Register 0
PVMAP00_1 – Port 00 Configuration Register 1
Bit[7:0]:
Bit[7:0]:
Bit[7:0]:
Bit[7:0]:
Bit[7:0]:
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81)
VLAN Mask for ports 7 to 0 (Default FF)
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00)
PVID [7:0] (Default is FF)
VLAN Mask for ports 15 to 8 (Default is FF)
2
2
2
2
C (R/W)
C (R/W)
C (R/W)
C (R/W)
Zarlink Semiconductor Inc.
ZL50416
57
Data Sheet