zl50416 Zarlink Semiconductor, zl50416 Datasheet - Page 70

• Manufacturer Part Number: zl50416
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.7.5
CPU Address:h304
Accessed by CPU
Bit [7:0] Byte 4 of the CPU MAC address. (Default 00)
13.7.6
CPU Address:h305
Accessed by CPU
Bit [7:0] Byte 5 of the CPU MAC address. (Default 00).
13.7.7
CPU Address:h306
Accessed by CPU, serial interface (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0xFF)
13.7.8
CPU Address:h310
Accessed by CPU, serial interface (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0xFF)
Bit [0]: Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic counter wraps
around. Refer to hardware statistic counter for interrupt sources.
Bit [1]: Port 0 link change mask
Bit [4]: Port 1 statistic counter wrap around interrupt mask. Refer to hardware statistic counter for interupt sources.
Bit [5]: Port 1 link change mask
Bit [7:0]MASK
Bit [0]:
Bit [1]:
Bit [2]:
Bit [7:3]:
- 1: Mask the interrupt
- 0: Unmask the interrupt (Enable interrupt)
- 1: Mask the interrupt
- 0: Unmask the interrupt
MAC4 – CPU Mac address byte 4
MAC5 – CPU Mac address byte 5
INT_MASK0 – Interrupt Mask 0
INTP_MASK0 – Interrupt Mask for MAC Port 0,1
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7
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read
Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read
Reserved
6
5
P1
4
Zarlink Semiconductor Inc.
ZL50416
3
70
2
1
P0
0
Data Sheet