kfm2g16q2a-deb8 Samsung Semiconductor, Inc., kfm2g16q2a-deb8 Datasheet - Page 103

• Manufacturer Part Number: kfm2g16q2a-deb8
• Description: 2gb Muxonenand A-die
• Manufacturer: Samsung Semiconductor, Inc.

3.9.5 Handshaking Operation During Synchronous Burst Block Read Mode
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst
data is ready to be read.
To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see Section
2.8.19, "System Configuration1 Register").
The rising edge of RDY which is derived at the same cycle of data fetch clock indicates the initial word of valid burst data.
Synchronous Burst Block Read Operation Flow Chart
NOTE :
1) These registers must be set as BSA=1000, BSC=00 and FSA=00.
2) INT auto mode is mandatory for Synchronous Burst Block Read Operation.
3) For the continuous synchronous burst block read, only INT PIN is availabe.
4) While reading data from DataRAM, all normal synchronous burst read mode is supported for the main area.
5) At this time, host should disable the CE of OneNAND in order to operate another device. Even if host does not operate another device,
MuxOneNAND2G(KFM2G16Q2A-DEBx)
MuxOneNAND4G(KFN4G16Q2A-DEBx)
For the other fixed number of words linear burst block read, both INT register and INT pin are avilable.
CE should be disabled during INT low.
Write 0 to INT register or PIN
Wait for INT register or PIN
Write ‘BSA’, ‘BSC’ of Flash
Add: F107h DQ=FPA, FSA
Add: F100h DQ=DFS*, FBA
Add: F200h DQ=BSA, BSC
Write ‘DFS, FBA’ of Flash
Write ‘FPA, FSA’ of Flash
Write Synchronous Burst
Select DataRAM for DDP
Add: F241h DQ[15]=INT
Add=F220h DQ=000Ah
Add: F241h DQ=0000h
Block Read Command
Add: F101h DQ=DBS*
low to high transition
Host reads data from
Add: F104h DQ=FPC
Write ‘FPC’ of Flash
DataRAM 0
Start
4)
1)
1)
3)
2)3)
CE of OneNAND is disabled
Wait for INT register or PIN
Wait for INT register or PIN
Add: F241h DQ[15]=INT
Add: F241h DQ[15]=INT
final page set by FPC?
high to low transition
low to high transition
Host reads data from
another device while
Finished reading
Host may operate
Synchronous Burst Block
DataRAM 1
- 103 -
Read Fail
YES
4)
3)
3)
5)
NO
NO
CE of OneNAND is disabled
Wait for INT register or PIN
Wait for INT register or PIN
Add: F240h DQ[10]=1(Error)
Synchronous Burst Block
* DBS, DFS is for DDP
Add: F241h DQ[15]=INT
Add: F241h DQ[15]=INT
final page set by FPC?
high to low transition
low to high transition
another device while
Host reads data from
Host may operate
Finished reading
Read Completed
Read Controller
Status Register
DataRAM 0
DQ[10]=0?
FLASH MEMORY
YES
YES
4)
3)
3)
5)
NO