kfm2g16q2a-deb8 Samsung Semiconductor, Inc., kfm2g16q2a-deb8 Datasheet - Page 122

• Manufacturer Part Number: kfm2g16q2a-deb8
• Description: 2gb Muxonenand A-die
• Manufacturer: Samsung Semiconductor, Inc.

3.14.1 OTP Block Load Operation
An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer, thus
making the OTP contents available to the Host.
The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of a Flash
Block Address (FBA) command.
After being accessed with the OTP Access Command, the contents of OTP memory area are loaded using the same operations as a normal
load operation to the NAND Flash Array memory (see section 3.6 for more information).
To exit the OTP access mode following an OTP Block Load Operation, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is per-
formed.
OTP Block Read Operation Flow Chart
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address in a single die package.
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1.
MuxOneNAND2G(KFM2G16Q2A-DEBx)
MuxOneNAND4G(KFN4G16Q2A-DEBx)
FBA must be an address of a chip containing OTP block that is supposed to be accessed in DDP
Write ‘OTP Access’ Command
Write ‘BSA, BSC’ of DataRAM
Write 0 to interrupt register
Write ‘DFS*, FBA’ of Flash
Add: F100h DQ=DFS*, FBA
Add: F200h DQ=BSA, BSC
Add: F107h DQ=FPA, FSA
Select DataRAM for DDP
Write ‘FPA, FSA’ of Flash
Add: F241h DQ[15]=INT
Add: F241h DQ=0000h
Add: F220h DQ=0065h
Add: F101h DQ=DBS*
low to high transition
Wait for INT register
Start
* DBS, DFS is for
1)
2)
- 122 -
Write 0 to interrupt register
OTP Reading completed
/NAND Flash Core Reset
Add: F241h DQ[15]=INT
Write ‘Load’ Command
Add: F241h DQ=0000h
low to high transition
Host reads data from
Wait for INT register
DQ=0000h or 0013h
Do Cold/Warm/Hot
Add: F220h
DataRAM
OTP Exit
2)
FLASH MEMORY