kfm2g16q2a-deb8 Samsung Semiconductor, Inc., kfm2g16q2a-deb8 Datasheet - Page 11

• Manufacturer Part Number: kfm2g16q2a-deb8
• Description: 2gb Muxonenand A-die
• Manufacturer: Samsung Semiconductor, Inc.

2.4 Pin Description
NOTE :
Do not leave power supply(Vcc-Core/Vcc-IO, V
MuxOneNAND2G(KFM2G16Q2A-DEBx)
MuxOneNAND4G(KFN4G16Q2A-DEBx)
Host Interface
Power Supply
etc.
ADQ15~ADQ0
Pin Name
V
V
CC
/ Vccq
RDY
/ Vcc
DNU
CLK
AVD
CC
V
INT
WE
RP
CE
OE
NC
-Core
SS
-IO
Type
I/O
O
O
I
I
I
I
I
I
Multiplexed Address/Data bus
Interrupt
Notifies the Host when a command is completed. After power-up, it is at hi-z condition. Once IOBE is set to 1,
it does not float to hi-z condition even when CE is disabled or OE is disabled. Especially, in case of DDP,
when reset(Cold, Warm, Hot, NAND Flash Core) command and ‘2X program’ command(007Dh) issued, it
operates as open drain output with internal resistor (~50Kohm).
Ready
Indicates data valid in synchronous read modes and is activated while CE is low.
RDY pin may not be used in Non-Handshaking Mode. (Refer to Chapter 7.1)
Clock
CLK synchronizes the device to the system bus frequency in synchronous read mode.
The first rising edge of CLK in conjunction with AVD low latches address input.
Write Enable
WE controls writes to the bufferRAM and registers. Data is latched on the WE pulse’s rising edge
Address Valid Detect
Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are
latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on CLK’s ris-
ing edge while AVD is held low for one clock cycle.
> Low : for asynchronous mode, indicates valid address ;for burst mode,
> High : device ignores address inputs
Reset Pin
When low, RP resets internal operation of MuxOneNAND. RP status is don’t care during power-up
and bootloading.
When high, RP level must be equivalent to Vcc-IO / Vccq level.
Chip Enable
CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,
and places A/DQ in Hi-Z
Output Enable
OE-low enables the device’s output data buffers during a read cycle.
Power for MuxOneNAND Core
This is the power supply for MuxOneNAND Core.
Power for MuxOneNAND I/O
This is the power supply for MuxOneNAND I/O
Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc.
Ground for MuxOneNAND
Do Not Use
Leave it disconnected. These pins are used for testing.
No Connection
Lead is not internally connected.
- Inputs for addresses during read operation, which are for addressing BufferRAM & Register.
- Inputs data during program and commands for all operations, outputs data during memory array/
register read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are disabled.
causes starting address to be latched on rising edge on CLK
SS
) disconnected.
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Name and Description
FLASH MEMORY