kfm2g16q2a-deb8 Samsung Semiconductor, Inc., kfm2g16q2a-deb8 Datasheet - Page 112

• Manufacturer Part Number: kfm2g16q2a-deb8
• Description: 2gb Muxonenand A-die
• Manufacturer: Samsung Semiconductor, Inc.

2X Interleave Cache Program Operation Flow Diagram
NOTE :
1) DBS must be set before data input.
2) FBA must be an even block.
3) These registers must be set as BSA=1000, BSC=00 and FSA=00.
4) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1.
5) Host is strongly recommended to see the INT register(F241h) of each chip.
6) Once ‘2X PGM command’ is issued onto a chip, the same command(2X PGM) must be issued onto another chip.
7) If error bit is set at this step, DQ[1]~[4] shoulde be checked in order to find where the error occurred.
MuxOneNAND2G(KFM2G16Q2A-DEBx)
MuxOneNAND4G(KFN4G16Q2A-DEBx)
If not, Samsung can not gurantee the following operation.
*
Add: DataRAM DQ=Data(4KB)
Write 0 to Interrupt register
Write ‘BSA’, ‘BSC’ of Flash
Add: F100h DQ=DFS, FBA
Write Data into DataRAM0,1
Add: F107h DQ=FPA, FSA
Add: F200h DQ=BSA, BSC
Write 2X Cache PGM CMD
* DBS, DFS is for DDP
Select DataRAM for DDP
Write ‘DFS, FBA’ of Flash
Write ‘FPA, FSA’ of Flash
Add: F220h DQ=007Fh
Add: F241h DQ=0000h
If program operation
results in an error,
map out the block
including the page in
error and copy the
target data to another
block.
Add: F101h DQ=DBS
Is it first input
for a chip
Start
YES
1)
3)
2)
3)
4)
NO
NO
NO
Add: DataRAM DQ=Data(4KB)
Write 0 to Interrupt register
DQ[4],[2]=Plane1,2 previous
Write ‘BSA’, ‘BSC’ of Flash
Write Data into DataRAM0,1
Add: F100h DQ=DFS, FBA
Add: F107h DQ=FPA, FSA
Select DataRAM for DDP
Add: F200h DQ=BSA, BSC
Write ‘DFS, FBA’ of Flash
Write ‘FPA, FSA’ of Flash
Add: F241h DQ=8040h
Add: F220h DQ=007Dh
Add: F241h DQ=0000h
Add: F101h DQ=DBS
Write 2X PGM CMD
Last 2 Plane PGM
Check INT register
DQ[4] | DQ[2] = 0?
Read Controller
Status Register
if it is ready
Add: F240h
for a chip?
Map Out
YES
YES
5)
6)
1)
3)
2)
3)
4)
- 112 -
NO
Add: DataRAM DQ=Data(4KB)
Write 0 to Interrupt register
Write ‘BSA’, ‘BSC’ of Flash
DQ[4],[2]=Plane1,2 previous
Add: F100h DQ=DFS, FBA
Write Data into DataRAM0,1
Add: F107h DQ=FPA, FSA
Select DataRAM for DDP
Add: F200h DQ=BSA, BSC
Write ‘DFS, FBA’ of Flash
Write ‘FPA, FSA’ of Flash
Add: F240h DQ[10]=Error
low to high transition
Add: F220h DQ=007Dh
Add: F241h DQ=0000h
Add: F241h DQ=8040h
Add: F241h DQ=8040h
Wait for INT register
Add: F101h DQ=DBS
Write 2X PGM CMD
Check INT register
DQ[4] | DQ[2] = 0?
Status Register
Read Controller
Read Controller
Status Register
if it is ready
Add: F240h
YES
5)
7)
6)
4)
1)
3)
2)
3)
4)
NO
NO
Select DataRAM for DDP
Add: F240h DQ[10]=Error
FLASH MEMORY
Add: F241h DQ=8040h
Add: F101h DQ=DBS
Check INT register
Status Register
Read Controller
if it is ready
DQ[10]=0?
DQ[10]=0?
complete
YES
YES
5)
7)
1)