ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 102

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

On-chip peripherals
Note:
102/188
Table 56.
SPI Data I/O Register (SPIDR)
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see
SPIDR
Bit
2
1
0
R/W
D7
7
Name
Warning:
SOD
SSM
SSI
SPICSR register description (continued)
SPI Output Disable
SS Management
SS Internal mode
R/W
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1).
1: SPI output disabled.
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See
on page
0: Hardware management (SS managed by external pin).
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O).
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS slave select signal when the SSM bit is set.
0: Slave selected.
1: Slave deselected.
D6
6
A write to the SPIDR register places data directly into the
shift register for transmission.
Figure
93.
R/W
D5
5
50).
R/W
D4
4
Function
R/W
D3
3
R/W
D2
2
Slave Select management
Reset value: undefined
R/W
D1
1
ST72324B
R/W
D0
0