ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 115

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
10.5.5
10.5.6
10.5.7
Low power modes
Table 59.
Interrupts
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
Table 60.
SCI registers
SCI Status Register (SCISR)
Table 61.
Transmit data register empty
Transmission complete
Received data ready to be read
Overrun error detected
Idle line detected
Parity error
SCISR
Bit Name
Mode
Wait
7
Halt
TDRE
RO
7
TDRE
Interrupt event
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Effect of low power modes on SCI
SCI interrupt control/wake-up capability
SCISR register description
Transmit Data Register Empty
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a write to the SCIDR register).
0: Data is not transferred to the shift register.
1: Data is transferred to the shift register.
Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.
RO
TC
6
RDRF
RO
5
Event flag Enable control bit Exit from WAIT Exit from HALT
RDRF
TDRE
IDLE
OR
TC
PE
IDLE
RO
4
Description
Function
TCIE
ILIE
RIE
PIE
TIE
OR
RO
3
RO
NF
2
Reset value: 1100 0000 (C0h)
Yes
Yes
Yes
Yes
Yes
Yes
On-chip peripherals
RO
FE
1
No
No
No
No
No
No
115/188
RO
PE
0