ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 96

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

On-chip peripherals
10.4.4
Note:
Note:
96/188
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see
(OVR) on page
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 54
The diagram may be interpreted as a master or slave timing diagram where the SCK, MISO
and MOSI pins are directly connected between the master and the slave device.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Figure 54. Data clock timing diagram
1. This figure should not be used as a replacement for parametric information. Refer to the Electrical
Characteristics chapter.
(from master)
Figure
(from slave)
MISO
(from slave)
SCK
(CPOL = 0)
MOSI
(CPOL = 1)
SCK
(CPOL = 0)
(CPOL = 1)
(to slave)
Capture strobe
(from master)
Capture strobe
SCK
MISO
MOSI
SCK
SS
(to slave)
SS
shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
97).
54).
MSB
MSB
MSB
MSB
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
(1)
CPHA = 0
Bit 4
CPHA = 1
Bit 4
Bit 4
Bit 4
Bit3
Bit3
Bit3
Bit3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
LSB
LSB
LSB
Overrun condition
LSB
ST72324B