ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 87

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
Table 50.
Input Capture 1 High Register (IC1HR)
This is an 8-bit register that contains the high part of the counter value (transferred by the
input capture 1 event).
IC1HR
1:0
Bit Name
6
5
4
3
2
MSB
RO
7
OCF1
OCF2
TIMD
ICF2
TOF
-
Output Compare Flag 1
Timer Overflow Flag
Input Capture Flag 2
Output Compare Flag 2
Timer Disable
Reserved, must be kept cleared.
CSR register description (continued)
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
0: No input capture (reset value).
1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
register, then read or write the low byte of the IC2R (IC2LR) register.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC2R (OC2LR) register.
This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce
power consumption. Access to the timer registers is still available, allowing the timer
configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled.
1: Timer prescaler, counter and outputs disabled.
RO
6
RO
5
RO
4
Function
RO
3
RO
2
On-chip peripherals
Reset value: undefined
RO
1
LSB
RO
0
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