ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 118

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

On-chip peripherals
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Table 62.
SCI Control Register 2 (SCICR2)
Table 63.
SCICR2
Bit
Bit
7
6
5
4
1
0
R/W
TIE
7
Name
Name
TCIE
ILIE
PIE
RIE
TIE
PS
SCICR1 register description (continued)
SCICR2 register description
Parity Selection
Parity Interrupt Enable
Transmitter Interrupt Enable
Transmission Complete Interrupt Enable
Receiver interrupt Enable
Idle Line Interrupt Enable
TCIE
R/W
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
6
R/W
RIE
5
R/W
ILIE
4
Function
Function
R/W
TE
3
R/W
RE
2
Reset value: 0000 0000 (00h)
RWU
R/W
1
ST72324B
SBK
R/W
0