ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 43

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
7.6
7.6.1
External interrupts
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register
sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
●
●
●
●
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
Figure 22. External interrupt control bits
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
(Figure
PF2
PB4
PA3
PB3
Port F [2:0] interrupts
Port B4 interrupt
Port A3 interrupt
Port B [3:0] interrupts
PFDDR.2
PBDDR.4
PADDR.3
PBDDR.3
PBOR.4
PFOR.2
PAOR.3
PBOR.3
22). This control allows up to four fully independent external interrupt source
IPA BIT
IPB BIT
IS20
IS10
IS20
IS10
Sensitivity
Sensitivity
Sensitivity
Sensitivity
control
control
control
EICR
EICR
control
EICR
EICR
IS21
IS11
IS21
IS11
PF2
PF1
PF0
PB3
PB2
PB1
PB0
ei1 interrupt source
ei3 interrupt source
ei0 interrupt source
ei2 interrupt source
Interrupts
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