sed1374 ETC-unknow, sed1374 Datasheet - Page 177

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Page 1
SED1374 Register Summary
SED1374 Register Summary
Table Bypass
Disp Status
REG[00h] R
REG[01h] M
REG[02h] M
REG[03h] M
REG[04h] H
REG[05h] V
REG[06h] V
REG[07h] FPL
REG[08h] H
REG[09h] FPF
REG[0Ah] V
Vert Non-
REG[0Bh] MOD R
REG[0Ch] S
REG[0Dh] S
REG[0Fh] S
REG[10h] S
REG[12h] M
TFT/STN
reserved
Look-Up
Bit 15
Bit 5
Bit 1
Bit 7
Bit 7
Bit 7
Bit 7
n/a
n/a
n/a
n/a
n/a
n/a
Bit-Per-Pixel
EVISION
ORIZONTAL
ERTICAL
ERTICAL
ORIZONTAL
CREEN
CREEN
ODE
Dual/Single Color/Mono
ODE
ODE
ERTICAL
CREEN
CREEN
EMORY
INE
RAME
Bit 14
Bit 14
Bit 4
Bit 0
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
n/a
n/a
n/a
n/a
n/a
n/a
n/a
R
R
R
3
S
ATE
EGISTER
EGISTER
EGISTER
2 S
2 S
1 S
1 S
TART
A
C
P
P
S
N
DDRESS
ODE
ANEL
ANEL
TART
ON
TART
TART
R
TART
TART
P
N
EGISTER
ANEL
ON
Screen 1 Start Word Address = (REG[0Ch], REG[0Dh])
P
-D
Performance
Screen 2 Start Word Address = (REG[0F], REG[10h])
R
Product Code = 000110
0
1
2
OSITION
S
S
ISPLAY
EGISTER 1
-D
P
W
W
W
W
Vertical Panel Size = (REG[05h], REG[06h]) + 1
High
IZE
IZE
OSITION
Bit 13
Bit 13
Bit 3
IO address = FFE1h, RW
IO address = FFE2h, RW
IO address = FFE3h, RW
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
O
Bit 5
ISPLAY
ORD
ORD
n/a
S
n/a
n/a
n/a
ORD
ORD
FFSET
IZE
R
R
IO address = FFEBh, RW
5
EGISTER
EGISTER
P
A
A
A
A
R
IO address = FFE7h, RW
ERIOD
DDRESS
DDRESS
DDRESS
DDRESS
EGISTER
3
P
R
IO address = FFE9h, RW
Screen 2 Start Word Address
ERIOD
IO address = FFE0h
EGISTER
Div (CLKI/2)
Input Clock
Memory Address Offset
Horizontal Panel Size = 8(REG + 1)
Polarity
FPLine
(LSB)
(MSB)
R
Bit 12
Bit 12
Bit 2
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
n/a
n/a
EGISTER
R
R
R
R
Screen 1 Start Word Address
IO address = FFE8h, RW
EGISTER
IO address = FFE4h, RW
EGISTER
EGISTER
EGISTER
IO address = FFF2h, RW
IO address = FFE5h, RW
IO address = FFE6h, RW
Horizontal Non-Display Period = 8(REG + 4)
Vertical Non-Display Period
FPLine Start Position = 8(REG[07h] + 2)
IO address = FFEAh, RW
LCDPWR
FPFrame Start Position
(LSB)
(MSB)
FPFrame
(LSB)
(MSB)
Override
Polarity
Display
Blank
Bit 11
Bit 11
Bit 1
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
n/a
2
MOD Rate
, RO
IO address = FFEFh, RW
IO address = FFECh, RW
IO address = FFF0h, RW
IO address = FFEDh, RW
PS Enable
Hardware
FPSHIFT
Repeat
Frame
Mask
Bit 10
Bit 10
Bit 0
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
n/a
Hw Video
Enable
Revision Code = 00
Invert
Vertical Panel Size
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 9
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 9
Bit 1
Sw Power Save
Bit 9
Data Width
Video Invert
Software
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
4
6
Notes
1 These bits are used to identify the SED1373 at power on / reset.
2 IO addresses are relative to the beginning of display memory.
3 Gray Shade/Color Mode Selection
SwivelView
REG[13h] S
REG[14h] S
REG[15h] L
REG[16h] L
REG[17h] L
REG[18h] GPIO C
REG[19h] GPIO S
REG[1Ah] S
REG[1Bh] S
Mode En.
REG[1Ch] L
Color/Mono
REG[01] bit 5
Bit 7
Bit 7
Bit 7
n/a
n/a
n/a
n/a
n/a
n/a
1
0
CREEN
CREEN
OOK
OOK
OOK
CRATCH
WIVEL
INE
SwivelView
Mode Sel.
Bit 6
-U
-U
-U
Bit 6
B
Bit 6
n/a
n/a
n/a
n/a
n/a
n/a
YTE
V
P
P
P
ONFIGURATION
TATUS
Bit-Per-Pixel Bit 1
1 V
1 V
IEW
T
T
T
P
REG[02] bit 7
ABLE
ABLE
ABLE
C
AD
ERTICAL
ERTICAL
M
OUNT
/ C
R
ODE
A
B
D
EGISTER
0
1
0
1
ONTROL
Screen 1 Vertical Size = (REG[13h], REG[14h])
DDRESS
ANK
ATA
R
Bit 5
Bit 1
Bit 1
Bit 5
Bit 5
R
n/a
Red Bank Select
n/a
n/a
n/a
n/a
S
S
EGISTER
EGISTER
IZE
IZE
C
RGB Index
S
R
ELECT
EGISTER
ONTROL
R
R
R
IO address = FFFAh, RW
R
EGISTER
EGISTER
EGISTER
EGISTER
IO address = FFFCh, RW
GPIO4 Pin
GPIO4 Pin
IO Config
IO Status
IO address = FFFBh, RW
R
Scratch Pad Register
Bit-Per-Pixel Bit 0
EGISTER
R
Bit 4
Bit 0
Bit 0
Bit 4
Bit 4
IO address = FFF7h, RW
n/a
n/a
n/a
EGISTER
Line Byte Count
REG[02] bit 6
(LSB)
(MSB)
7
IO address = FFF9h, RW
IO address = FFF5h, RW
0
1
0
1
0
1
0
1
IO address = FFF6h, RW
IO address = FFF4h, RW
IO address = FFF8h, RW
IO address = FFF3h, RW
GPIO3 Pin
GPIO3 Pin
IO Config
IO Status
Green Bank Select
Bit 3
Bit 3
Bit 1
Bit 3
Bit 3
Bit 3
n/a
n/a
16 Gray Shade
2 Gray Shade
4 Gray Shade
GPIO2 Pin
GPIO2 Pin
Look-Up Table Address
IO Config
IO Status
reserved
256 Colors
16 Colors
Look-Up Table Data
2 Colors
4 Colors
Bit 2
Bit 2
Bit 0
Bit 2
Bit 2
Bit 2
n/a
Display Mode
reserved
GPIO1 Pin
GPIO1 Pin
SwivelView Mode PCLK
IO Config
IO Status
Screen 1 Vertical Size
Bit 1
Bit 9
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Blue Bank Select
1 Bit-Per-Pixel
2 Bit-Per-Pixel
4 Bit-Per-Pixel
8 Bit-Per-Pixel
1 Bit-Per-Pixel
2 Bit-Per-Pixel
4 Bit-Per-Pixel
Select
GPIO0 Pin
GPIO0 Pin
IO Config
IO Status
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
4 Panel Data Format
5 High Performance Selection
6 Power Save Mode Selection
7 Look-Up Table Access
TFT/STN
REG[01]
bit 7
High Performance
Color/Mono
REG[01h]
Power Save Bit 1
0
1
bit 5
0
1
1
1
1
0
1
0
0
1
1
Color/
Mono
REG[01]
bit 5
0
1
bit 5
X
0
0
1
1
REG[15h]
REG[02] bit 7
Bit-Per-Pixel
don’t care
Dual/
Single
REG[01]
bit 6
Bit 1
0
1
X
0
1
0
1
bit 4
Power Save Bit 0
X
0
1
0
1
0
1
0
1
Look-Up Table Selected
Green/Gray Look-Up Table
Green/Gray Look-Up Table
Data
Width
Bit 1
REG[01]
bit 1
REG[02] bit 6
Bit-Per-Pixel
Blue Look-Up Table
Red Look-Up Table
0
1
0
1
0
1
0
1
Auto-Increment
Bit 0
0
1
0
1
X
Data
Width
Bit 0
REG[01]
bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Software Power Save Mode
MClk = PClk/8
MClk = PClk/4
MClk = PClk/2
MClk = PClk
Normal Operation
X26A-R-001-02
X26A-R-001-02
Color Single 8-bit LCD Format 1
Color Single 8-bit LCD Format 2
reserved
reserved
G[n], G[n+1], G[n+2]...
R[n], G[n], B[n] R[n+1], G[n+1],...
R[n], R[n+1], R[n+2]...
G[n], G[n+1], G[n+2]...
B[n], B[n+1], B[n+2]...
Display Modes
Mode
MClk = PClk
Mono Single 4-bit LCD
Mono Single 8-bit LCD
Color Single 4-bit LCD
Mono Dual 8-bit LCD
Color Dual 8-bit LCD
12 bit TFT Panel
9 bit TFT Panel
99/04/23
Pointer Sequence
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Function
1 bit-per-pixel
2 bit-per-pixel
4 bit-per-pixel
8 bit-per-pixel