sed1374 ETC-unknow, sed1374 Datasheet - Page 384
sed1374
Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1374.pdf
(420 pages)
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Page 10
3 System Design Using the ITE IT8368E PC Card Buffer
3.1 Hardware Description
SED1374
X26A-G-012-01
PR31500/PR31700
IT8368E
LHA[23]/MFIO[10]
LHA[22]/MFIO[9]
LHA[21]/MFIO[8]
LHA[20]/MFIO[7]
LHA[19]/MFIO[6]
LHA[15:13]/
MFIO[2:0]
/CARDxWAIT
DCLKOUT
HD[23:16]
HD[31:24]
HA[12:0]
ENDIAN
If the system designer uses the ITE IT8368E PC Card and multiple-function I/O buffer, the
SED1374 can be interfaced so that it ’shares’ a PC Card slot. The SED1374 is mapped to a rarely-
used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the SED1374
virtually transparent to PC Card devices that use the same slot.
The ITE8368E has been specially designed to support EPSON LCD controllers. The ITE IT8368E
provides eleven Multi-Function IO pins (MFIO). Configuration registers may be used to allow these
MFIO pins to provide the control signals required to implement the SED1374 CPU interface.
The PR31500/PR31700 processor only provides addresses A[12:0], therefore devices requiring
more address space must use an external device to latch A[25:13]. The IT8368E’s MFIO pins can
be configured to provide this latched address.
Figure 3-1: SED1374 to PR31500/PR31700 Connection Using an IT8368E
V
DD
Clock divider
pull-up
Interfacing to the Philips MIPS PR31500/PR31700 Processor
...or...
Oscillator
System RESET
EPSON Research and Development
+3.3V
See text
Vancouver Design Center
RESET#
AB[12:0]
AB[15:13]
DB[7:0]
DB[15:8]
WAIT#
BS#
WE1#
WE0#
RD1#
RD0#
CS#
IO V
CLKI
BCLK
Issue Date: 98/11/09
SED1374
DD
, CORE V
DD
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