sed1374 ETC-unknow, sed1374 Datasheet - Page 41

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
7.1.6 Generic #2 Interface Timing
Hardware Functional Specification
Issue Date: 99/04/29
Symbol
WE#,RD#
T
A[15:0]
D[15:0]
f
D[15:0]
BCLK
WAIT#
BHE#
(write)
BCLK
BCLK
t10
(read)
t1
t2
t3
t4
t5
t6
t7
t8
t9
CS#
Bus Clock frequency
Bus Clock period
WE# low to D[15:0] valid (write cycle)
D[15:0] valid to WAIT# high (read cycle)
RD# high to D[15:0] high impedance (read cycle)
A[15:0], BHE#, CS# valid to WE#, RD# low
WE#, RD# high to A[15:0], BHE#, CS# invalid
WE# high to D[15:0] invalid (write cycle)
RD# low to D[15:0] driven (read cycle)
WE#, RD# low to WAIT# driven low
BCLK to WAIT# high
WE#, RD# high to WAIT# high impedance
Hi-Z
Hi-Z
Hi-Z
T
BCLK
Note
t1
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
t8
t5
t3
Figure 7-6: Generic #2 Timing
Table 7-6: Generic #2 Timing
Parameter
VALID
t9
VALID
t6
1/f
VALID
Min
BCLK
0
0
0
0
0
T
Max
BCLK
10
50
16
14
16
11
t4
t2
t10
X26A-A-001-02
t7
Units
SED1374
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Hi-Z
Hi-Z