sed1374 ETC-unknow, sed1374 Datasheet - Page 93

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
13.3 Power Save Mode Function Summary
13.4 Panel Power Up/Down Sequence
Hardware Functional Specification
Issue Date: 99/04/29
Note
After chip reset or when entering/exiting a power save mode, the Panel Interface signals
follow a power on/off sequence shown below. This sequence is essential to prevent damage
to the LCD panel.
FPDAT[11:0], FPSHIFT (see note)
When FPDAT[11:8] are designated as GPIO outputs, the output state prior to enabling
the Power Save Mode is maintained. When FPDAT[11:8] are designated as GPIO in-
puts, unused inputs must be tied to either IO V
face Pin Mapping,” on page 23.
Sequence Controller Running?
FPLINE, FPFRAME, DRDY
Memory Access Possible?
IO Access Possible?
Display Active?
Table 13-4: Power Save Mode Function Summary
LCDPWR
Power Save
Forced Low
Forced Low
Hardware
Inactive
No
No
No
No
DD
Power Save
Forced Low
Forced Low
Software
Inactive
or GND - see Table 5-3: “LCD Inter-
Yes
Yes
No
No
Normal
Active
Active
Active
Yes
Yes
Yes
Yes
X26A-A-001-02
SED1374
Page 85