sed1374 ETC-unknow, sed1374 Datasheet - Page 49

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sed1374

Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet

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Epson Research and Development
Vancouver Design Center
7.3.5 Single Color 4-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Hardware Functional Specification
Issue Date: 99/04/29
DRDY (MOD)
DRDY (MOD)
FPDAT[7:4]
FPFRAME
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
FPSHIFT
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPLINE
FPLINE
1-R1
1-B1
1-R2
1-G1
Figure 7-14: Single Color 4-Bit Panel Timing
1-G2
1-R3
1-B2
1-G3
LINE1
1-B3
1-R4
1-G4
1-B4
LINE2
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
LINE3
LINE4
VDP
HDP
LINE479 LINE480
1-R320
1-B319
1-G320
1-B320
VNDP
HNDP
LINE1
LINE2
X26A-A-001-02
SED1374
Page 41

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