sed1374 ETC-unknow, sed1374 Datasheet - Page 265

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

EPSON Research and Development
Vancouver Design Center
2.2 Memory Mapping and Aliasing
2.3 SED1374 Configuration and Pin Mapping
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
Configuration
SED1374
CNF[2:0]
CNF3
BS#
Pin
= configuration for Toshiba TX3912 host bus interface
Note
The SED1374 requires an addressing space of 64K bytes. The on-chip display memory occupies the
range 0 through 9FFFh. The registers occupy the range FFE0h through FFFFh. The TX3912
demultiplexed address lines A16 and above are ignored, thus the SED1374 is aliased 1024 times at
64K byte intervals over the 64M byte PC Card slot #1 memory space. In this example
implementation, the TX3912 control signal CARDREG* is ignored, the SED1374 also takes up the
entire PC Card slot 1 configuration space.
The SED1374 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the SED1374
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to the direct connection approach.
When the SED1374 is configured for “Generic #2” interface, the host interface pins are mapped as
in the table below.
If aliasing is undesirable, additional decoding circuitry must be added.
Table 2-2: SED1374 Generic #2 Interface Pin Mapping
Table 2-1: SED1374 Configuration for Direct Connection
Generic #2
Big Endian
1 (IO V
Value hard wired on this pin is used to configure:
DD
Pin Name
)
RD/WR#
WE1#
WE0#
BS#
RD#
Connect to IO V
Connect to IO V
111: Generic #1 or #2
Pin Function
BHE#
WE#
RD#
DD
DD
Little Endian
Generic #1
0 (V
SS
)
X26A-G-004-01
SED1374
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