sed1374 ETC-unknow, sed1374 Datasheet - Page 347

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sed1374

Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet

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Epson Research and Development
Vancouver Design Center
4 MPC821 to SED1374 Interface
4.1 Hardware Description
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
Figure 4-1: Typical Implementation of MPC821 to SED1374 Interface
The interface between the SED1374 and the MPC821 requires minimal glue logic. One
inverter is required to change the polarity of the WAIT# signal (an active low signal) to
insert wait states in the bus cycle. The MPC821 Transfer Acknowledge signal (TA) is an
active low signal which ends the current bus cycle. The inverter is enabled using CS# so
that TA is not driven by the SED1374 during non-SED1374 bus cycles. A single resistor is
used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected to
GND).
The following diagram shows a typical implementation of the MPC821 to SED1374
interface.
MPC821
A[16:31]
SYSCLK
D[0:15]
RESET
TA
WE0
WE1
CS4
OE
Vcc
470
BUSCLK
RESET#
RD/WR#
SED1374
AB15-AB0
RD#
WAIT#
WE1#
DB[15:D0]
CS#
WE0#
X26A-G-010-02
SED1374
Page 15

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