sed1374 ETC-unknow, sed1374 Datasheet - Page 65

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
bit 4
bit 3
bit 2
bit 1
bit 0
Hardware Functional Specification
Issue Date: 99/04/29
Note
Note
Input Clock Divide
When this bit = 0, the operating clock(CLK) is same as the input clock (CLKI). When this
bit = 1, CLK = CLKI/2.
In landscape mode PCLK=CLK and MCLK is selected as per Table 8-3: “High Perfor-
mance Selection”.
In SwivelView mode MCLK and PCLK are derived from CLK as shown in Table 8-9:
“Selection of PCLK and MCLK in SwivelView Mode,” on page 69.
Display Blank
This bit blanks the display image. When this bit = 1, the display is blanked (FPDAT lines
to the panel are driven low). When this bit = 0, the display is enabled.
Frame Repeat (EL support)
This feature is used to improve Frame Rate Modulation of EL panels. When this bit = 1,
an internal frame counter runs from 0 to 3FFFFh. When the frame counter rolls over, the
modulated image pattern is repeated (every 1 hour when the frame rate is 72Hz). When
this bit = 0, the modulated image pattern is never repeated.
Hardware Video Invert Enable
In passive panel modes (REG[01h] bit 7 = 0) FPDAT11 is available as either GPIO4 or
hardware video invert. When this bit = 1, Hardware Video Invert is enabled via the
FPDAT11 pin. When this bit = 0, FPDAT11 operates as GPIO4. See Table 8-4: “Inverse
Video Mode Select Options” below.
Software Video Invert
When this bit = 1, Inverse video mode is selected. When this bit = 0, standard video mode
is selected. See Table 8-4: “Inverse Video Mode Select Options” below.
Video data is inverted after the Look-Up Table.
Video data is inverted after the Look-Up Table.
Hardware Video
Invert Enable
0
0
1
1
Table 8-4: Inverse Video Mode Select Options
Software Video
Active Panels)
(Passive and
Invert
X
X
0
1
(Passive Panels
FPDAT11
Only)
X
X
0
1
Video Data
Normal
Inverse
Normal
Inverse
X26A-A-001-02
SED1374
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