sed1374 ETC-unknow, sed1374 Datasheet - Page 247

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
6.2 Non-ISA Bus Support
6.3 Embedded Memory Support
6.4 Decode Logic
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26
!CS = (Address >= ^hD0000) & (Address <= ^hDFFFF) & REFRESH & !RESET;
!MEMCS16= (Address1 >= ^h0C0000) & (Address1 <= ^h0DFFFF);
RESET_
Note
The SDU1374B0C board is specifically designed to support the standard 16-bit ISA bus;
however, the SED1374 directly supports many other host bus interfaces. Header strips H1
and H2 are provided and contain all the necessary IO pins to interface to these host buses.
See CPU/Bus Interface Connector Pinouts on page 11; Table 2-1: “Configuration DIP
Switch Settings,” on page 8; and Table 2-3: “Jumper Settings,” on page 9 for details.
When using the header strips to provide the bus interface observe the following:
• All IO signals on the ISA bus card edge must be isolated from the ISA bus (do not plug
• U7, a TIBPAL16L8-15 PAL, is currently used to provide the SED1374 CS# (pin 74),
The SED1374 contains 40K bytes of 16-bit SRAM used for the display buffer. The SRAM
starting address is set at D0000h. Starting at this address, the board design decodes a 64K
byte segment accommodating both the 40K byte display buffer and the SED1374 internal
register set.
The SED1374 registers are mapped into the upper 32 bytes of the 64K byte segment
(DFFE0h to DFFFFh).
All the required decode logic is provided through a TIBPAL16L8-15 PAL (U7, socketed).
This PAL contains the following equations.
the card into a computer). Voltage lines are provided on the header strips.
RESET# (pin 73) and other decode logic signals for ISA bus use. This functionality
must now be provided externally; remove the PAL from its socket to eliminate conflicts
resulting from two different outputs driving the same input. Refer to Table 5-1: “Host
Bus Interface Pin Mapping” for connection details.
When using a 3.3V host bus interface, IOVDD must be set to 3.3V by setting jumper
(JP1) to the 2-3 position. Refer to Table 2-3: “Jumper Settings,” on page 9.
= !RESET;
X26A-G-005-01
SED1374
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