MC68HC05P9ACDW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P9ACDW Datasheet - Page 108

• Manufacturer Part Number: MC68HC05P9ACDW
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SIOP
PB5/SDO
PB6/SDI
108
Figure 61
input, and data output. The state of the serial clock between
transmissions is a logic 1. The first falling edge on the PB7/SCK pin
signals the beginning of a transmission, and data appears at the
PB5/SDO pin. Data is captured at the PB6/SDI pin on the rising edge of
the serial clock, and the transmission ends on the eighth rising edge of
the serial clock.
The PB5/SDO pin is the SIOP data output. Between transfers, the state
of the PB5/SDO pin reflects the value of the last bit shifted out on the
previous transmission, if there was one. To preset the beginning state,
write to the corresponding port data bit before enabling the SIOP. On the
first falling edge on the PB7/SCK pin, the first data bit to be shifted out
appears at the PB5/SDO pin.
The PB6/SDI pin is the SIOP data input. Valid SDI data must be present
for an SDI setup time, t
must remain valid for an SDI hold time, t
serial clock. (See
Freescale Semiconductor, Inc.
(MSB-FIRST OPTION)
(LSB-FIRST OPTION)
For More Information On This Product,
SERIAL CLOCK
SAMPLE INPUT
DATA OUTPUT
DATA OUTPUT
shows the timing relationships among the serial clock, data
Go to: www.freescale.com
Figure 61. SIOP Data/Clock Timing
Table 22
MSB
LSB
SIOP
S
, before the rising edge of the serial clock and
BIT 6
BIT 1
and
BIT 5
BIT 2
Table
BIT 4
BIT 3
23.)
H
, after the rising edge of the
BIT 3
BIT 4
BIT 2
BIT 5
BIT 1
BIT 6
10-mc68hc05p9a
MOTOROLA
MSB
LSB