MC68HC05P9ACDW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P9ACDW Datasheet - Page 77

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MC68HC05P9ACDW

Manufacturer Part Number
MC68HC05P9ACDW
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Data Direction
Register D (DDRD)
17-mc68hc05p9a
MOTOROLA
NOTE:
Data direction register D determines whether each port D pin is an input
or an output.
DDRD5 — Data Direction Register D Bit
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 40
Writing a logic 1 to a DDRD bit enables the output buffer for the
corresponding port D pin; a logic 0 disables the output buffer.
Reset:
$0007
Read:
Write:
This read/write bit controls the data direction of pin PD5. Reset clears
DDRD5, configuring PD5 as an input.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = PD5 configured as output
0 = PD5 configured as input
READ DATA DIRECTION REGISTER D ($0007)
WRITE DATA DIRECTION REGISTER D ($0007)
WRITE PORT D DATA REGISTER ($0003)
READ PORT D DATA REGISTER ($0003)
Bit 7
0
0
shows the I/O logic of port D.
Figure 39. Data Direction Register D (DDRD)
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= Unimplemented
Parallel I/O Ports
6
0
0
Figure 40. Port D I/O Logic
DDRD5
5
0
RESET
4
0
0
DDRDx
PDx
3
0
0
2
0
0
Parallel I/O Ports
1
0
0
Bit 0
Port D
0
0
77
PDx

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