MC68HC05P9ACDW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P9ACDW Datasheet - Page 70

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MC68HC05P9ACDW

Manufacturer Part Number
MC68HC05P9ACDW
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Parallel I/O Ports
Port A I/O Pin
Interrupts/Pullups
Port B
Port B Data
Register (PORTB)
70
NOTE:
NOTE:
Function:
Alternate
If the port A interrupt/pullup enabled mask option is selected the
PA0–PA7 pins will function as external interrupt pins when configured as
inputs. (See
Port B is a 3-bit I/O port that shares its pins with the serial I/O port
(SIOP).
Do not use port B for general-purpose I/O while the SIOP is enabled.
The port B data register contains a latch for each of the three port B pins.
PB[7:5] — Port B Data Bits
Writing to data direction register B does not affect the data direction of
port B pins that are being used by the SIOP. However, data direction
register B always determines whether reading port B returns the states
of the latches or the states of the pins.
Reset:
$0001
Read:
Write:
These read/write bits are software programmable bits. Data direction
of each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 7
SCK
PB7
Figure 32. Port B Data Register (PORTB)
Go to: www.freescale.com
External Interrupt
= Unimplemented
Parallel I/O Ports
PB6
SDI
6
SDO
PB5
5
Unaffected by reset
on page 53.)
4
0
3
0
2
0
1
0
10-mc68hc05p9a
MOTOROLA
Bit 0
0

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