MC68HC05P9ACDW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P9ACDW Datasheet - Page 72

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MC68HC05P9ACDW

Manufacturer Part Number
MC68HC05P9ACDW
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Parallel I/O Ports
72
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
of the port B pins.
Freescale Semiconductor, Inc.
For More Information On This Product,
READ DATA DIRECTION REGISTER B ($0005)
WRITE DATA DIRECTION REGISTER B ($0005)
WRITE PORT B DATA REGISTER ($0001)
READ PORT B DATA REGISTER ($0001)
Data Direction Bit
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
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Parallel I/O Ports
0
1
Table 16. Port B Pin Operation
Figure 34. Port B I/O Logic
I/O Pin Mode
Input, Hi-Z
Output
RESET
Table 16
(1)
DDRBx
PBx
Accesses to Data Bit
Read
Latch
Pin
summarizes the operation
Latch
Write
Latch
(2)
12-mc68hc05p9a
MOTOROLA
PBx

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