MC68HC05P9ACDW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P9ACDW Datasheet - Page 71

• Manufacturer Part Number: MC68HC05P9ACDW
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Data Direction
Register B (DDRB)
11-mc68hc05p9a
MOTOROLA
NOTE:
NOTE:
SCK — Serial Clock
SDI — Serial Data Input
SDO — Serial Data Output
Data direction register B determines whether each port B pin is an input
or an output.
Enabling and then disabling the SIOP configures data direction register
B for SIOP operation and can also change the port B data register. After
disabling the SIOP, initialize data direction register B and the port B data
register as your application requires.
DDRB[7:5] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 34
Reset:
$0005
Read:
Write:
When the SIOP is enabled, SCK is the SIOP clock output (in master
mode) or the SIOP clock input (in slave mode).
When the SIOP is enabled, SDI is the SIOP data input.
When the SIOP is enabled, SDO is the SIOP data output.
These read/write bits control port B data direction. Reset clears
DDRB[7:5], configuring all three port B pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
DDRB7
Bit 7
0
shows the I/O logic of port B.
Figure 33. Data Direction Register B (DDRB)
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= Unimplemented
DDRB6
Parallel I/O Ports
6
0
DDRB5
5
0
4
0
0
3
0
0
2
0
0
Parallel I/O Ports
1
0
0
Bit 0
Port B
0
0
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