MC68HC05P9ACDW FREESCALE [Freescale Semiconductor, Inc], MC68HC05P9ACDW Datasheet - Page 68

• Manufacturer Part Number: MC68HC05P9ACDW
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Parallel I/O Ports
Data Direction
Register A (DDRA)
68
NOTE:
Data direction register A determines whether each port A pin is an input
or an output.
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 31
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
of the port A pins.
Reset:
$0004
Read:
Write:
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all eight port A pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
DDRA7
Bit 7
0
Data Direction Bit
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
shows the I/O logic of port A.
Figure 30. Data Direction Register A (DDRA)
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DDRA6
Parallel I/O Ports
0
1
6
0
Table 15. Port A Pin Operation
DDRA5
5
0
I/O Pin Mode
Input, Hi-Z
Output
DDRA4
4
0
Table 16
(1)
DDRA3
3
0
Accesses to Data Bit
Read
Latch
Pin
summarizes the operation
DDRA2
2
0
Latch
Write
Latch
DDRA1
(2)
1
0
8-mc68hc05p9a
MOTOROLA
DDRA0
Bit 0
0