PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 118

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F45J10 FAMILY
11.1
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 11-1:
FIGURE 11-2:
DS39682C-page 116
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T1CKI
T1OSO/T1CKI
Timer1 Operation
T1OSI
T1OSI
Timer1 Oscillator
Timer1 Oscillator
T1OSCEN
T1OSCEN
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
(1)
(1)
TMR1CS
TMR1CS
(CCP Special Event Trigger)
Clear TMR1
(CCP Special Event Trigger)
Clear TMR1
Clock
Internal
Clock
F
Internal
F
OSC
OSC
/4
/4
Preliminary
On/Off
1
0
1
0
Timer1 Clock Input
Timer1 Clock Input
Prescaler
Prescaler
1, 2, 4, 8
1, 2, 4, 8
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T1CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
2
2
OSC
TMR1L
TMR1L
/4). When the bit is set, Timer1 increments
8
8
Synchronize
Synchronize
Sleep Input
Sleep Input
Detect
Detect
High Byte
High Byte
TMR1H
TMR1
TMR1
8
© 2007 Microchip Technology Inc.
8
8
Internal Data Bus
1
0
1
0
Read TMR1L
Write TMR1L
Set
TMR1IF
on Overflow
Set
TMR1IF
on Overflow
Timer1
Timer1
On/Off
On/Off