PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 286

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F45J10 FAMILY
21.2.2
ADDFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39682C-page 284
Q Cycle Activity:
Note:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
EXTENDED INSTRUCTION SET
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
=
=
ADDFSR 2, 23h
literal ‘k’
Add Literal to FSR
ADDFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
None
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
1
1
Read
1110
Q2
03FFh
0422h
1000
Process
Data
Q3
ffkk
Write to
FSR
kkkk
Q4
Preliminary
ADDULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Operation
Decode
FSR2
PC
FSR2
PC
Q1
No
=
=
=
=
Operation
ADDULNK 23h
literal ‘k’
Add Literal to FSR2 and Return
ADDULNK k
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
1
2
Read
1110
Q2
No
03FFh
0100h
0422h
(TOS)
© 2007 Microchip Technology Inc.
1000
Operation
Process
Data
Q3
No
11kk
Operation
Write to
FSR
kkkk
Q4
No