PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 126

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F45J10 FAMILY
13.1
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
13.1.1
The CCP modules utilize Timers 1 or 2, depending on
the mode selected. Timer1 is available to modules in
Capture or Compare modes, while Timer2 is available
for modules in PWM mode.
TABLE 13-1:
TABLE 13-2:
DS39682C-page 124
CCP1 Mode CCP2 Mode
Note 1:
Compare
Compare
Compare
Capture
Capture
Capture
PWM
PWM
PWM
ECCP/CCP Mode
Compare
Capture
(1)
(1)
(1)
CCP Module Configuration
PWM
Includes standard and Enhanced PWM operation.
CCP MODULES AND TIMER
RESOURCES
Compare
Compare
Compare
Capture
Capture
Capture
PWM
PWM
ECCP/CCP MODE – TIMER
INTERACTIONS BETWEEN ECCP1/CCP1 AND CCP2 FOR TIMER RESOURCES
RESOURCE
PWM
(1)
(1)
CCP2 can be configured for the Special Event Trigger to reset TMR1. Automatic A/D
conversions on the trigger event can also be done. Operation of ECCP1/CCP1 will be
affected.
ECCP1/CCP1 can be configured for the Special Event Trigger to reset TMR1. Operation
of CCP2 will be affected.
Either module can be configured for the Special Event Trigger to reset TMR1. Automatic
A/D conversions on the CCP2 trigger event can be done.
None
None
None
None
Each module uses TMR1 as the time base.
Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Timer Resource
Timer1
Timer1
Timer2
Preliminary
Both modules may be active at any given time and may
share the same timer resource if they are configured to
operate in the same mode (Capture/Compare or PWM)
at the same time. The interactions between the two
modules
Figure 13-2. In Timer1 in Asynchronous Counter mode,
the capture operation will not work.
13.1.2
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device config-
uration. The CCP2MX configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the configuration bit
is cleared, CCP2 is multiplexed with RB3.
Changing the pin assignment of CCP2 does not auto-
matically change any requirements for configuring the
port pin. Users must always verify that the appropriate
TRIS register is configured correctly for CCP2
operation regardless of where it is located.
Interaction
are
CCP2 PIN ASSIGNMENT
summarized
© 2007 Microchip Technology Inc.
in
Figure 13-1
and