PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 352

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F45J10 FAMILY
Timing Diagrams
DS39682C-page 350
A/D Conversion ......................................................... 326
Acknowledge Sequence ........................................... 179
Asynchronous Reception .......................................... 200
Asynchronous Transmission ..................................... 198
Asynchronous Transmission (Back to Back) ............ 198
Automatic Baud Rate Calculation ............................. 196
Auto-Wake-up Bit (WUE) During Normal Operation . 201
Auto-Wake-up Bit (WUE) During Sleep .................... 201
Baud Rate Generator with Clock Arbitration ............. 173
BRG Overflow Sequence .......................................... 196
BRG Reset Due to SDAx Arbitration During Start
Brown-out Reset (BOR) ............................................ 314
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCLx = 0).... 182
Bus Collision During a Stop Condition (Case 1) ....... 184
Bus Collision During a Stop Condition (Case 2) ....... 184
Bus Collision During Start Condition (SDAx Only) .... 181
Bus Collision for Transmit and Acknowledge............ 180
Capture/Compare/PWM (Including ECCP Module) .. 316
CLKO and I/O ........................................................... 313
Clock Synchronization .............................................. 166
Clock/Instruction Cycle ............................................... 51
EUSART Synchronous Receive (Master/Slave) ....... 325
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ...................... 317
Example SPI Master Mode (CKE = 1) ...................... 318
Example SPI Slave Mode (CKE = 0) ........................ 319
Example SPI Slave Mode (CKE = 1) ........................ 320
External Clock (All Modes Except PLL) .................... 311
Fail-Safe Clock Monitor............................................. 239
First Start Bit Timing ................................................. 174
Full-Bridge PWM Output ........................................... 137
Half-Bridge PWM Output .......................................... 136
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ................................ 110
Parallel Slave Port (PSP) Write ................................ 110
PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Dis-
PWM Auto-Shutdown (PRSEN = 1, Auto-Restart En-
PWM Direction Change ............................................ 139
PWM Direction Change at Near 100% Duty Cycle ... 139
PWM Output ............................................................. 128
Repeated Start Condition.......................................... 175
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................. 321
C Bus Start/Stop Bits.............................................. 321
C Master Mode (7 or 10-Bit Transmission) ............ 177
C Master Mode (7-Bit Reception) ........................... 178
C Slave Mode (10-Bit Reception, SEN = 0) ........... 163
C Slave Mode (10-Bit Reception, SEN = 1) ........... 168
C Slave Mode (10-Bit Transmission)...................... 164
C Slave Mode (7-bit Reception, SEN = 0).............. 161
C Slave Mode (7-Bit Reception, SEN = 1) ............. 167
C Slave Mode (7-Bit Transmission)........................ 162
C Slave Mode General Call Address Sequence (7 or
C Stop Condition Receive or Transmit Mode ......... 179
Condition........................................................... 182
(Case 1) ............................................................ 183
(Case 2) ............................................................ 183
(Master/Slave)................................................... 325
10-Bit Address Mode) ....................................... 169
abled) ................................................................ 142
abled) ................................................................ 142
2
2
C Bus Data ......................................... 323
C Bus Start/Stop Bits ......................... 323
Preliminary
Timing Diagrams and Specifications
Top-of-Stack Access........................................................... 48
TRISE Register
TSTFSZ ............................................................................ 281
Two-Speed Start-up.................................................. 229, 237
Two-Word Instructions
TXSTA Register
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................. 202
Slave Synchronization .............................................. 151
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode).......................................... 150
SPI Mode (Slave Mode, CKE = 0) ............................ 152
SPI Mode (Slave Mode, CKE = 1) ............................ 152
Synchronous Reception (Master Mode, SREN) ....... 205
Synchronous Transmission ...................................... 203
Synchronous Transmission (Through TXEN) ........... 204
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Tied to
Timer0 and Timer1 External Clock ........................... 315
Transition for Entry to Idle Mode................................. 35
Transition for Entry to SEC_RUN Mode ..................... 32
Transition for Entry to Sleep Mode ............................. 34
Transition for Two-Speed Start-up (INTRC) ............. 237
Transition for Wake from Idle to Run Mode ................ 35
Transition for Wake from Sleep .................................. 34
Transition from RC_RUN Mode to PRI_RUN Mode ... 33
Transition to RC_RUN Mode ...................................... 33
A/D Conversion Requirements ................................. 327
AC Characteristics
Capture/Compare/PWM Requirements (Including
CLKO and I/O Requirements.................................... 313
EUSART Synchronous Receive Requirements........ 325
EUSART Synchronous Transmission Requirements 325
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Slave Mode,
Example SPI Slave Mode Requirements (CKE = 1). 320
External Clock Requirements ................................... 311
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements............................. 316
PLL Clock ................................................................. 312
Reset, Watchdog Timer, Oscillator Start-up Timer,
Timer0 and Timer1 External Clock Requirements.... 315
PSPMODE Bit........................................................... 103
Example Cases........................................................... 52
BRGH Bit .................................................................. 191
2
2
C Bus Data Requirements (Slave Mode) ............... 322
C Bus Start/Stop Bits Requirements (Slave Mode) 321
(OST) and Power-up Timer (PWRT) ................ 314
V
Tied to V
Tied to V
V
Internal RC Accuracy........................................ 312
ECCP Module).................................................. 316
CKE = 0) ........................................................... 317
CKE = 1) ........................................................... 318
CKE = 0) ........................................................... 319
Power-up Timer and Brown-out Reset
Requirements ................................................... 314
DD
DD
, V
Rise > T
DD
2
2
DD
DD
C Bus Data Requirements ................. 324
C Bus Start/Stop Bits Requirements.. 323
Rise Tpwrt) ......................................... 40
), Case 1 .......................................... 40
), Case 2 .......................................... 41
PWRT
© 2007 Microchip Technology Inc.
) ............................................. 41
DD
,