PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 159

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 15-4:
© 2007 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: SCKx Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1000 = I
0111 = I
0110 = I
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Legend:
R = Readable bit
-n = Value at POR
SSPxCON1: MSSPx CONTROL REGISTER 1 (I
WCOL
R/W-0
Note:
transmission to be started (must be cleared in software)
cleared in software)
cleared in software)
2
2
2
2
2
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Firmware Controlled Master mode (Slave Idle)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
When enabled, the SDAx and SCLx pins must be properly configured as input or
output.
SSPOV
R/W-0
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
Preliminary
OSC
R/W-0
CKP
PIC18F45J10 FAMILY
/(4 * (SSPxADD + 1))
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
2
C™ MODE)
SSPM2
2
R/W-0
C conditions were not valid for a
x = Bit is unknown
SSPM1
R/W-0
DS39682C-page 157
SSPM0
R/W-0
bit 0