PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 187

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PIC18F24J10-E/ML

Manufacturer Part Number
PIC18F24J10-E/ML
Description
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
TABLE 15-4:
© 2007 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISD
SSP1BUF
SSP1ADD
SSP1CON1
SSP1CON2
SSP1STAT
SSP2BUF
SSP2ADD
SSP2CON1
SSP2CON2
SSP2STAT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
Note 1:
Name
(1)
These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
MSSP1 Baud Rate Reload Register (I
MSSP2 Baud Rate Reload Register (I
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
GIE/GIEH PEIE/GIEL TMR0IE
PSPIE
PSPIP
PSPIF
OSCFIF
OSCFIE
OSCFIP
TRISC7
TRISD7
SSP2IF
SSP2IE
SSP2IP
WCOL
WCOL
GCEN
GCEN
SMP
SMP
Bit 7
REGISTERS ASSOCIATED WITH I
(1)
(1)
(1)
ACKSTAT
ACKSTAT
TRISC6
TRISD6
BCL2IE
BCL2IP
SSPOV
SSPOV
BCL2IF
CMIF
CMIE
CMIP
ADIE
ADIP
Bit 6
ADIF
CKE
CKE
TRISC5
TRISD5
SSPEN
ACKDT
SSPEN
ACKDT
RCIF
RCIE
RCIP
Bit 5
D/A
D/A
2
2
C™ Slave mode).
C Slave mode).
TRISC4
TRISD4
ACKEN
ACKEN
Preliminary
INT0IE
2
2
Bit 4
TXIF
TXIE
TXIP
CKP
CKP
C Master mode).
C Master mode).
P
P
2
C™ OPERATION
PIC18F45J10 FAMILY
SSP1IF
SSP1IE
SSP1IP
BCL1IE
BCL1IP
TRISC3
TRISD3
BCL1IF
SSPM3
SSPM3
RCEN
RCEN
RBIE
Bit 3
S
S
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
TRISD2
SSPM2
SSPM2
Bit 2
PEN
R/W
PEN
R/W
TMR2IE
TMR2IP
TMR2IF
TRISC1
TRISD1
SSPM1
SSPM1
INT0IF
RSEN
RSEN
Bit 1
UA
UA
2
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP2IF
TRISC0
TRISD0
C™ mode.
SSPM0
SSPM0
RBIF
DS39682C-page 185
Bit 0
SEN
SEN
BF
BF
on Page
Values
Reset
43
45
45
45
45
45
45
45
45
45
46
46
44
44
44
44
46
46
46
46
44
46

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