PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 214
![no-image](/images/no-image-200.jpg)
PIC18F24J10-E/ML
Manufacturer Part Number
PIC18F24J10-E/ML
Description
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F24J10-EML.pdf
(358 pages)
- Current page: 214 of 358
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(V
V
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 17-1:
DS39682C-page 212
REF
DD
+ and RA2/AN2/V
and V
Note 1:
SS
2:
), or the voltage level on the RA3/AN3/
Converter
10-Bit
Channels AN5 through AN7 are not available in 28-pin devices.
I/O pins have diode protection to V
A/D
Reference
Voltage
A/D BLOCK DIAGRAM
REF
-/CV
REF
pins.
V
V
REF
REF
+
-
(Input Voltage)
VCFG1:VCFG0
V
AIN
Preliminary
DD
and V
X
X
1
0
0
1
V
X
X
SS
DD
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 17-1.
.
(2)
V
SS
(2)
CHS3:CHS0
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
© 2007 Microchip Technology Inc.
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
(1)
(1)
(1)
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