PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 90

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F45J10 FAMILY
8.4
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 8-10:
DS39682C-page 88
IPR Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit
1 = High priority
0 = Low priority
CCP1IP: ECCP1/CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
PSPIP
R/W-1
Note:
(1)
This bit is not implemented on 28-pin devices and should be read as ‘0’.
R/W-1
ADIP
R/W-1
RCIP
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-1
TXIP
SSP1IP
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
CCP1IP
R/W-1
© 2007 Microchip Technology Inc.
x = Bit is unknown
TMR2IP
R/W-1
TMR1IP
R/W-1
bit 0