PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 27

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

2.4
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by setting the PLLEN bit in the
OSCTUNE register (Register 2-1).
REGISTER 2-1:
© 2007 Microchip Technology Inc.
PLL Frequency Multiplier
bit 7
bit 6
bit 5-0
OSCTUNE: PLL CONTROL REGISTER
Unimplemented: Read as ‘0’
PLLEN: Frequency Multiplier PLL Enable bit
1 = PLL enabled
0 = PLL disabled
Unimplemented: Read as ‘0’
bit 7
Legend:
R = Readable bit
-n = Value at POR
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is
U-0
—
unavailable and read as ‘0’.
PLLEN
R/W-0
(1)
(1)
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
PIC18F45J10 FAMILY
U-0
—
FIGURE 2-4:
OSC2
OSC1
HSPLL or ECPLL (CONFIG2L)
(1)
PLL Enable (OSCTUNE)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HS or EC
U-0
—
Mode
F
F
÷4
IN
OUT
PLL BLOCK DIAGRAM
U-0
—
Comparator
Loop
Filter
Phase
VCO
x = Bit is unknown
U-0
—
DS39682C-page 25
SYSCLK
U-0
—
bit 0