PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 237

• Manufacturer Part Number: PIC18F24J10-E/ML
• Description: 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

20.2
For PIC18F45J10 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 20-1:
REGISTER 20-9:
TABLE 20-2:
© 2007 Microchip Technology Inc.
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
WDTPS3:WDTPD0
Name
All Device Resets
INTRC Oscillator
Watchdog Timer (WDT)
SWDTEN
CLRWDT
bit 7-1
bit 0
Sleep
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
WDT BLOCK DIAGRAM
WDTCON: WATCHDOG TIMER CONTROL REGISTER
bit 7
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Legend:
R = Readable bit
-n = Value at POR
Note 1: This bit has no effect if the configuration bit, WDTEN, is enabled.
U-0
—
Bit 6
Enable WDT
—
—
WDT Counter
U-0
—
Bit 5
—
—
÷128
INTRC Control
4
U-0
Bit 4
—
Preliminary
Programmable Postscaler
RI
—
W = Writable bit
‘1’ = Bit is set
1:1 to 1:32,768
U-0
Bit 3
PIC18F45J10 FAMILY
—
TO
—
20.2.1
The WDTCON register (Register 20-9) is a readable
and writable register. The SWDTEN bit enables or
disables WDT operation.
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
Bit 2
U-0
PD
WDT
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
(1)
POR
Bit 1
—
U-0
—
SWDTEN
Bit 0
BOR
x = Bit is unknown
U-0
—
DS39682C-page 235
Wake-up from
Power-Managed
Modes
WDT
Reset
Reset Values
SWDTEN
on page
R/W-0
44
44
bit 0
(1)