PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 194

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
TABLE 11-9:
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39977C-page 194
RE5/CANTX
RE6/RX2/DT2
RE7/TX2/CK2
Legend:
Note 1:
PORTE
LATE
TRISE
PADCFG1
ANCON0
Legend: Shaded cells are not used by PORTE.
Note 1:
Pin Name
Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Unavailable for 40 and 44-pin devices (PIC18F4XK0).
Alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration
bit is cleared.
Unimplemented on 44-pin devices, read as ‘ 0 ’.
ANSEL7
TRISE7
RE7
LATE7
RDPU
CANTX
Bit 7
PORTE FUNCTIONS (CONTINUED)
Function
RE5
RE6
RX2
RE7
CK2
DT2
TX2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1,2)
ANSEL6
Setting
TRISE6
RE6
LATE6
REPU
TRIS
Bit 6
0
1
0
0
1
1
1
1
0
1
0
0
1
(1)
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
ANSEL5
RFPU
TRISE5
LATE5
RE5
Bit 5
I/O Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
(1)
ST
ST
ST
ST
ST
ST
(1)
Preliminary
LATE<5> data output.
PORTE<5> data input.
CAN bus TX.
LATE<6> data output.
PORTE<6> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
LATE<7> data output.
PORTE<7> data input.
Asynchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial clock output (EUSART module); user must
configure as an input.
Synchronous serial clock input (EUSART module); user must configure
as an input.
RGPU
ANSEL4
TRISE4
RE4
LATE4
Bit 4
(1)
(1)
ANSEL3
Bit 3
RE3
—
—
—
ANSEL2
TRISE2
Description
LATE2
Bit 2
RE2
—
 2011 Microchip Technology Inc.
ANSEL1
TRISE1
LATE1
Bit 1
RE1
—
CTMUDS
ANSEL0
TRISE0
LATE0
Bit 0
RE0