PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 256

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
18.8
A unique feature on board the CTMU module is its ability
to generate system clock independent output pulses
based on either an external voltage or an external
capacitor value. When using an external voltage, this is
accomplished using the CTDIN input pin as a trigger for
the pulse delay. When using an external capacitor
value, this is accomplished using the internal compara-
tor voltage reference module and Comparator 2 input
pin.The pulse is output onto the CTPLS pin. To enable
this mode, set the TGEN bit.
See
CTMUDS (PADCFG1<0>) is cleared, the pulse delay is
determined by the output of Comparator 2, and when it
is set, the pulse delay is determined by the input of
CTDIN. C
output pulse width on CTPLS. The pulse width is calcu-
lated by T = (C
current source measurement step (
“Current Source Calibration”
reference voltage (CV
FIGURE 18-5:
DS39977C-page 256
Figure 18-5
Creating a Delay with the CTMU
Module
DELAY
DELAY
is chosen by the user to determine the
for an example circuit. When
/I)*V , where I is known from the
REF
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY
GENERATION
).
C
CTED1
CTMUI
DELAY
) and V is the internal
Section 18.4.1
External Reference
EDG1
Preliminary
CV
External Comparator
Current Source
PIC18F66K80
REF
Comparator
CTMU
C2
An example use of the external capacitor feature is
interfacing with variable capacitive-based sensors,
such as a humidity sensor. As the humidity varies, the
pulse-width output on CTPLS will vary. An example use
of the CTDIN feature is interfacing with a digital sensor.
The CTPLS output pin can be connected to an input
capture pin and the varying pulse width measured to
determine the sensor’s output in the application.
To use this feature:
1.
2.
3.
4.
When CTMUDS is cleared, as soon as C
charges to the value of the voltage reference trip point,
an output pulse is generated on CTPLS. When
CTMUDS is set, as soon as CTDIN is set, an output
pulse is generated on CTPLS.
C1
If CTMUDS is cleared, initialize Comparator 2.
If CTMUDS is cleared, initialize the comparator
voltage reference.
Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
Set EDG1STAT.
CTDIN
CTPLS
CTMUDS
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DELAY