PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 318

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
21.4.4.5
When the CKP bit is cleared, the SCL output is forced
to ‘ 0 ’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I
FIGURE 21-14:
DS39977C-page 318
WR
SSPCON1
SDA
SCL
CKP
Clock Synchronization and
the CKP bit
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLOCK SYNCHRONIZATION TIMING
2
C master device has
DX
Master device
asserts clock
Preliminary
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure
Master device
deasserts clock
21-14).
2
C bus have deasserted SCL. This
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DX – 1