PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 438

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
27.2.6
The registers in this section are the same as described
in
for convenience.
REGISTER 27-56: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5
DS39977C-page 438
Mode 0
Mode 1,2
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Section 10.0 “Interrupts”
In CAN Mode 1 and 2, these bits are forced to ‘ 0 ’.
CAN INTERRUPT REGISTERS
bit 7
IRXIF: CAN Bus Error Message Received Interrupt Flag bit
1 = An invalid message has occurred on the CAN bus
0 = No invalid message on the CAN bus
WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = Activity on the CAN bus has occurred
0 = No activity on the CAN bus
ERRIF: CAN Module Error Interrupt Flag bit
1 = An error has occurred in the CAN module (multiple sources; refer to
0 = No CAN module errors
When CAN is in Mode 0:
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 2 has not completed transmission of a message
When CAN is in Mode 1 or 2:
TXBnIF: Any Transmit Buffer Interrupt Flag bit
1 = One or more transmit buffers have completed transmission of a message and may be reloaded
0 = No transmit buffer is ready for reload
TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit
1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 1 has not completed transmission of a message
TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit
1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 0 has not completed transmission of a message
When CAN is in Mode 0:
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1 = Receive Buffer 1 has received a new message
0 = Receive Buffer 1 has not received a new message
When CAN is in Mode 1 or 2:
RXBnIF: Any Receive Buffer Interrupt Flag bit
1 = One or more receive buffers has received a new message
0 = No receive buffer has received a new message
When CAN is in Mode 0:
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1 = Receive Buffer 0 has received a new message
0 = Receive Buffer 0 has not received a new message
When CAN is in Mode 1:
Unimplemented: Read as ‘ 0 ’
When CAN is in Mode 2:
FIFOWMIF: FIFO Watermark Interrupt Flag bit
1 = FIFO high watermark is reached
0 = FIFO high watermark is not reached
R/W-x
R/W-x
IRXIF
IRXIF
WAKIF
WAKIF
R/W-x
R/W-x
. They are duplicated here
W = Writable bit
‘1’ = Bit is set
ERRIF
ERRIF
R/W-x
R/W-x
Preliminary
TXB2IF
TXBnIF
R/W-x
R/W-x
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXB1IF
TXB1IF
R/W-x
R/W-x
(1)
(1)
TXB0IF
TXB0IF
R/W-x
R/W-x
Section 27.15.6 “Error Interrupt”
(1)
(1)
 2011 Microchip Technology Inc.
x = Bit is unknown
RXB1IF
RXBnIF
R/W-x
R/W-x
FIFOWMIF
RXB0IF
R/W-x
R/W-x
bit 0
)