PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 304

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F66K80 FAMILY
REGISTER 21-4:
DS39977C-page 304
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
2:
3:
4:
When enabled, the SDA and SCL pins must be configured as inputs.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
When SSPM<3:0> = 1001 , any reads or writes to the SSPADD SFR address actually access the
SSPMSK register.
This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit
is ‘ 1 ’).
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: SCK Release Control bit
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
SSPM<3:0>: Master Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1001 = Load SSPMSK register at SSPADD SFR address
1000 = I
0111 = I
0110 = I
SSPOV
R/W-0
transmission to be started (must be cleared in software)
software)
software)
SSPCON1: MSSP CONTROL REGISTER 1 (I
2
2
2
2
2
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Firmware Controlled Master mode (slave Idle)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(1)
R/W-0
CKP
Preliminary
OSC
/(4 * (SSPADD + 1))
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
(1)
(2)
(3,4)
2
C™ MODE)
SSPM2
R/W-0
(2)
2
C conditions were not valid for a
(2)
 2011 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
(2)
SSPM0
R/W-0
bit 0
(2)