PIC18F25K80 MICROCHIP [Microchip Technology], PIC18F25K80 Datasheet - Page 196

• Manufacturer Part Number: PIC18F25K80
• Manufacturer: MICROCHIP [Microchip Technology]

corresponding Data Direction and Output Latch registers
PIC18F66K80 FAMILY
11.8
PORTG is a 5-bit wide, bidirectional port. The
are TRISG and LATG.
PORTG is multiplexed with EUSART and CCP, ECCP,
Analog, Comparator and Timer input functions
(Table
have Schmitt Trigger input buffers. The open-drain
functionality for the UART can be configured using
ODCON.
Each of the PORTG pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is per-
formed by clearing bit, RGPU (PADCFG1<4>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an out-
TABLE 11-13: PORTG FUNCTIONS
DS39977C-page 196
RG0/RX1/DT1
RG1/CANTX
RG2/T3CKI
RG3/TX1/CK1
Legend:
Note 1:
Note:
Pin Name
11-13). When operating as I/O, all PORTG pins
2:
PORTG, TRISG and
LATG Registers
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared.
Default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set.
PORTG is only available on 64-pin
devices.
Function
T3CKI
CANTX
RG0
RG1
RG2
RG3
RX1
DT1
TX1
CK1
(2)
Setting
TRIS
0
1
1
0
1
0
1
0
0
1
x
0
1
0
0
1
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I/O Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATG<0> data output.
PORTG<0> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
LATG<1> data output.
PORTG<1> data input.
CAN bus TX.
LATG<2> data output.
PORTG<2> data input.
Timer3 clock input.
LATG<3> data output.
PORTG<3> data input.
Asynchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial clock output (EUSART module); user must
configure as an input.
Synchronous serial clock input (EUSART module); user must configure
as an input.
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
EXAMPLE 11-7:
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
04h
TRISG
Description
INITIALIZING PORTG
 2011 Microchip Technology Inc.
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as
; outputs
; RG2 as input
; RG4:RG3 as inputs