FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 116

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

The Watchdog Timer Control, SMI Enable and
SMI Status Registers can be accessed by the
host when the chip is in the normal run mode if
CR03 Bit[7]=1. The host uses GP Index and
Data register to access these registers. The
Power on default GP Index and Data registers
are
configuration mode the GP Index address may
be programmed to reside on addresses 0xE0,
0xE2, 0xE4 or 0xEA. The GP Data address is
automatically set to the Index address + 1. Upon
exiting the configuration mode the new GP Index
and
Data
0xEA
registers
and
REGISTER
GP Index
GP Data
0xEB
are
used
Table 46A - GP Index and Data Register
respectively.
Index address + 1
ADDRESS (R/W)
0xE0, E2, E4, EA
to
GP INDEX REGISTERS
access
In
116
registers WDT_CTRL, SMI Enable and SMI
Status Registers.
To access these registers when in normal (run)
mode, the host should perform an IOW of the
Register Index to the GP Index register (at
0xEX) to select the Register and then read or
write the Data register (at Index+1) to access
the register.
The WDT_CTRL, SMI Enable and SMI Status
registers can also be accessed by the host when
in the configuration state through Logical Device
8.
Access to Watchdog Timer
Control, SMI Enable and
SMI Status Registers (see
Table 46B)
NORMAL (RUN) MODE
0x01-0x0F