FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 158

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Floppy Data Rate
Select Shadow
UART1 FIFO
Control Shadow
UART2 FIFO
Control Shadow
PME Control
Default = 0x00 on
VTR POR
PME Status
Default = 0x00 on
VTR POR
NAME
Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
(R/w Clear)
(R/W)
0xC2
0xC3
0xC4
0xC5
0xC6
(R)
(R)
(R)
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by VCC POR, SOFT RESET
or HARD RESET
Bit[0] PME_Status
= 0 (default)
= 1 Set when FDC37M81x would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT
RESET or HARD RESET.
Writing a “1” to PME_Status will clear it and cause
the FDC37M81x to stop asserting nIO_PME, in
enabled. Writing a “0” to PME_Status has no effect.
(default)
signal
PCI nIO_PME signal, independent of the state
of the PME_En bit.
nIO_PME signal assertion is disabled
Enables FDC37M81x to assert nIO_PME
158
DEFINITION
STATE
C
C
C