FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 159

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

PME Wake Status
Default = 0x00 on
VTR POR
PME Wake Enable
Default = 0x00 on
V
TR
POR
NAME
Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
(R/w Clear)
(R/W)
0xC7
0xC8
This register indicates the state of the individual
PME wake sources, independent of the individual
source enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] Reserved
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[7:5] Reserved
The PME Wake Status register is not affected by
VCC POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[4:0] will clear it. Writing a “0” to
any bit in PME Wake Status Register has no effect.
This register is used to enable individual
FDC37M81x PME wake sources onto the nIO_PME
wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake
event and the PME_En bit is “1”, the source will
assert the PCI nIO_PME signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status
register will indicate the state of the wake source but
will not assert the PCI nIO_PME signal.
Bit[0] Reserved
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[7:5] Reserved
The PME Wake Enable register is not affected by
Vcc POR, SOFT RESET or HARD RESET.
159
DEFINITION
STATE