FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 138

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Note 1:
Note 2:
Note 3:
INDEX
0xF6 :
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xB5
0xB6
0xB7
0xF1
0xF2
0xF3
0xF4
FB
This register contains some bits that are read or write only.
Bit 0 is not cleared by HARD RESET.
The Parallel Port interrupt defaults to ‘1’ when the Parallel Port activate bit is cleared. When
the Parallel Port is activated, PINT follows the nACK input.
CLEAR
CLEAR
TYPE
R/W-
R/W-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
1
RESET
HARD
0x00
0x02
0x01
0x00
0x00
0x00
-
-
-
-
-
-
-
-
-
-
-
2
POR
VCC
0x00
0x00
0x00
0x02
0x01
0x00
0x00
0x00
0x00
-
-
-
-
-
-
-
-
RESET
SOFT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
138
POR
0x00
0x00
0x00
0x02
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
VTR
-
-
-
-
SMI Enable Register 2
SMI Status Register 1
SMI Status Register 2
Pin Multiplex Controls
Force Disk Change
Floppy Data Rate Select Shadow
UART1 FIFO Control Shadow
UART2 FIFO Control Shadow
PME Control Register
PME Status Register
PME Wake Status Register
PME Wake Enable Register
WDT_TIME_OUT
WDT_VAL
WDT_CFG
WDT_CTRL
Reserved
CONFIGURATION REGISTER