FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 157

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

SMI Status
Register 1
Default = 0x00
on VCC POR and
VTR POR
SMI Status
Register 2
Default = 0x00
on VCC POR and
VTR POR
Default = 0x00
on VTR POR
Pin Multiplex
Controls
Default = 0x02 on
VCC POR, VTR
POR and HARD
RESET
Force Disk Change
Default = 0x01 on
VCC POR
NAME
Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
0xB6 R/W
0xB7 R/W
0xB8 R/W
(R/W)
0xC0
0xC1
This register is used to read the status of the SMI
inputs.
The following bits must be cleared at their source.
Bit[0] Reserved
Bit[1] PINT (Parallel Port Interrupt)
The Parallel Port interrupt defaults to ‘1’ when the
Parallel Port activate bit is cleared.
Parallel Port is activated, PINT follows the nACK
input.
Bit[2] U2INT (UART 2 Interrupt)
Bit[3] U1INT (UART 1 Interrupt)
Bit[4] FINT (Floppy Disk Controller Interrupt)
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT (Watch Dog Timer)
This register is used to read the status of the SMI
inputs.
Bit[0] MINT: Mouse Interrupt. Cleared at source.
Bit[1] KINT: Keyboard Interrupt. Cleared at source.
Bit[2] IRINT: This bit is set by a transition on the IR
pin (RDX2 or IRRX as selected in CR L5-F1-B6 i.e.,
after the MUX). Cleared by a read of this register.
Bit[3] Reserved
Bit[4] P12: 8042 P1.2. Cleared at source
Bit[7:5] Reserved
Bits[7:0] Reserved
Bit[0] Reserved
Bit[1] DMA 3 Select
Bit[2] Reserved
Bit[3] 8042 Select
Bit[4] Reserved
Bit[5:7] Reserved
Bit[0] Force Change 0
0 = Inactive
1 = Active
Bit[7:1] Reserved
Force Change[0] can be written to 1 but is not
clearable by software.
Force Change 0 is cleared on nSTEP and nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND
Force Change 0) OR nDSKCHG
157
DEFINITION
When the
STATE
C,R
C
C
C