FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 130

• Manufacturer Part Number: FDC37M81
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

When using the keyboard and mouse for wakeup, it may be necessary to isolate the keyboard and
mouse signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep
states. This is due to the fact that the normal operation of the 8042 can prevent the system from
entering or exiting a sleep state or trigger false PME events. The FDC37M81x has “isolation” bits for
the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the
wakeup logic but block the keyboard clock and data signals and the mouse clock and data signals
from the 8042. These bits may be used when it is necessary to isolate the 8042 keyboard and mouse
signals from the 8042 before entering a system sleep state.
See the SMSC Application Note titled “Using the Enhanced Keyboard and Mouse Wakeup Feature in
SMSC Super I/O Parts” for more information.
The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device
7, Register 0xF0 (KRST_GA20) and are defined as follows:
Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal
to the mouse wakeup (PME) logic.
1= Block mouse clock and data signals into 8042
0= Do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT
signal to the keyboard wakeup (PME) logic.
1= Block keyboard clock and data signals into 8042
0= Do not block keyboard clock and data signals into 8042
When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon
exiting the sleep state. If either of the isolation bits is set prior to entering a sleep state where VCC
goes inactive (S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global
configuration register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing
0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing.
Caution: Bit 6 of
configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits in
register 0x2C, as this may produce undesired results.
It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not
go inactive (S1, S2).
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